
76
XMEGA A [MANUAL]
8077I–AVR–11/2012
6.8.2
CHnCTRL – Event Channel n Control register
Bit 7 – Reserved
This bit is reserved and will always be read as zero. For compatibility with future devices, always write this bit to zero
when this register is written.
Bit 6:5 – QDIRM[1:0]: Quadrature Decode Index Recognition Mode
These bits determine the quadrature state for the QDPH0 and QDPH90 signals, where a valid index signal is recognized
and the counter index data event is given according to
Table 6-5 on page 76. These bits should only be set when a
quadrature encoder with a connected index signal is used.These bits are available only for CH0CTRL, CH2CTRL, and
CH4CTRL.
Table 6-5.
QDIRM bit settings.
Bit 4 – QDIEN: Quadrature Decode Index Enable
When this bit is set, the event channel will be used as a QDEC index source, and the index data event will be enabled.
This bit is available only for CH0CTRL, CH2CTRL, and CH4CTRL.
Bit 3 – QDEN: Quadrature Decode Enable
Setting this bit enables QDEC operation.
This bit is available only for CH0CTRL, CH2CTRL, and CH4CTRL.
Bit 2:0 – DIGFILT[2:0]: Digital Filter Coefficient
These bits define the length of digital filtering used. Events will be passed through to the event channel only when the
event source has been active and sampled with the same level for the number of peripheral clock cycles defined by
DIGFILT.
Bit
7
6
54321
0
–
QDIRM[1:0]
QDIEN
QDEN
DIGFILT[2:0]
Read/Write
R
R/W
R
Initial Value
0
00000
0
QDIRM[1:0]
Index Recognition State
0
{QDPH0, QDPH90} = 0b00
0
1
{QDPH0, QDPH90} = 0b01
1
0
{QDPH0, QDPH90} = 0b10
1
{QDPH0, QDPH90} = 0b11